Minimize ATSR-1 Products and Algorithms
Minimize Processor Releases

The Level 1 and Level 2 processing was performed by RAL, using the components of the Archive Product Processor developed with funding from DECC. The SST L2P and L3U data were processed using the same ARC-based processor as was used for AATSR.

 

The processor configuration used in the Third Reprocessing of ATSR-1 data is:

  • Level 1 (TOA) processor: STEP/1.4
  • Level 2 (NR, AR) processor: Prt2-L/0.7
  • SST L2P processor: Rev 1735(M)

 

Auxiliary datafiles for ATSR-1 are available here.

(If downloading, note that some ADF names are not unique within the (A)ATSR multimission dataset)